SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. SR. SIGNAL ENGINEER - SERDES, SATELLITES (STARLINK) SpaceX is leveraging its experience in building rockets and spacecraft to deploy Starlink, the world’s most advanced broadband internet system. Starlink is the world’s largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system – thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We’ve only begun to scratch the surface of Starlink’s potential global impact. As we continue to upgrade and expand the constellation, we’re looking for best-in-class engineers to join the team. As a Signal and Power Integrity Engineer on Starlink’s Payload Engineering team, you’ll have SI and PI ownership throughout the entire life-cycle of the portfolio of hardware that enables this connectivity, and sits at the intersection of electrical, mechanical, thermal analysis, software, and antenna/RF engineering. Early in any given product’s design cycle, your work will include everything from IP evaluation in the silicon architecture stage, package performance evaluation, stackup material selection and characterization, channel and PDN architecture, and PCB layout oversight. Once hardware is in hand, you will drive troubleshooting, characterization, qualification, and general...
Responsibilities:
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Specify, design, simulate, verify, qualify, define production screens for, and generally troubleshoot SI and PI aspects of advanced satellite hardware, such as:
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Wireline and electro-optical communication systems with cutting edge (e.g. 10 to 112+ Gbps) SERDES, DSPs, retimers, and optoelectronics
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High-speed and high-bandwidth memory interfaces (DDR4, LPDDR5, GPDDR6, QSPI NOR, eMMC, etc.)
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Power needs and PDNs for the associated ASICs
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Work alongside RF engineers, antenna engineers, ASIC engineers, packaging engineers, mechanical engineers, thermal engineers, software engineers, supply chain, and production engineers (among others) to architect new products which will employ novel channels, interfaces, and power delivery strategies
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Derive top level specifications for PCB materials and channel subcomponents
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Design and optimize transition structures for the entire channel from die bump to die bump
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Drive detailed component selection to accompany your PDN designs
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Root cause and fix issues found in PCB manufacturing, PCBA test, or satellite integration
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Define best practices, simulation workflows, test methodologies, signoff criteria, and lab equipment needs for all SI/PI needs on Starlink satellite payloads
Requirements:
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Bachelor’s degree in electrical engineering, computer engineering, or physics
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5+ years of industry experience designing circuits, electronic products, or hardware
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2+ years of experience using one of the 3D EM simulation tools and high-speed digital channel simulators (CST, HFSS, ADS etc.)
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2+ years of research or industry experience with high-speed digital design or power integrity
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Master’s degree or PhD in electrical engineering, computer engineering with emphasis in electromagnetic theory, transmission line theory, wireline transceivers, or power integrity
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5+ years of electronic product experience designing hardware from concept through production; strong emphasis on full life-cycle development of new hardware products and not small incremental updates to legacy hardware
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5+ years of experience architecting, implementing, and debugging cutting edge DSP based SERDES products (i.e. 56Gbps, 112Gbps, 224Gbps) working across package and PCB
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5+ years of experience specifying, analyzing, debugging, and working with high speed, high bandwidth memory interfaces
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5+ years of experience designing, implementing, and debugging power delivery networks for large processors, FPGAs, SoC, or ASICs with complex power requirements
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Thorough understanding of wireline transceiver concepts, architectures, and circuits
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Strong understanding of computers and programming languages (Python, C/C++)
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Demonstrated ability to work in a highly cross-functional role